TLDR: TamperSec is on a mission to secure AI hardware against physical tampering, protecting sensitive models and data from advanced attacks and enabling international governance of AI. TamperSec is growing and looking to expand its capabilities by hiring an Electronic Engineer, Embedded Systems Engineer, and Business Development Lead. For more details, visit the TamperSec careers page!
The deadline to apply is 16 March at 11:59 PM Anywhere on Earth.
About TamperSec
TamperSec develops secure physical enclosures for AI hardware. The product prevents nanometer modifications at AI chips, stopping malicious actors from extracting confidential data, stealing AI model weights, or disabling on-chip governance mechanisms.
Key Responsibilities
- Hardware Design & Prototyping: Design tamper-detection elements including sensor layers, conductive trace
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That's correct.
That said, chip modifications are done on the same FIB machine. The cost estimate still seems accurate to me.
H100s are manufactured on TSMC's "3nm" node (a brand name), which has a Gate Pitch of 48 nm and a Metal Pitch of 24 nm. The minimum feature size is 9-12nm, according to Claude.
You are not at the physical limitations:
- Gallium-based FIB circuit edits can go down to ~7nm.
- Helium-based FIB circuit edits (~3...5x more expensive
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