A project from Verkor, a chip design startup. "Verkor is working with multiple of the top 10 fabless companies to deploy DC(Design Conductor; their AI agent for chip design) to accelerate their time to market".
I wonder how impressive this is for practitioners working on chip design. As a somewhat-adjacent amateur (I wrote some Verilog myself at all), it seems very impressive. I am a compiler practitioner (I was a committer to both LLVM and Rust) and I found Anthropic's Claude's C Compiler very impressive (to drop a name, Chris Lattner, the founder of LLVM, also found it impressive) and this seems similarly impressive.
I copied the full input to their system below. With that input and 12 hours, the system produced a decently working chip design. (While I can't see it myself lacking expertise in chip design, I expect it to be similarly "working" as Claude's C Compiler. CCC builds a bootable Linux kernel for multiple architectures, but it fails to reject programs with the simplest errors and has no diagnostics to speak of. It is in no way "production" quality.)
Note that apparent simplicity of input can be deceptive. If you think otherwise ask yourself whether you would have figured out the following problem from the paper:
We found that the input specification provided to DC has to be written in an extremely deliberate, tight, and verifiable/measurable manner. Without the CPI requirement in that document, for example, DC would sometimes generate a processor with significantly worse performance on branches and forwarding. With that line in the spec, DC would use a cycle counter in its testbench to compute its cycles per PC reported in the Spike trace to estimate CPI. In this way it was able to ensure it met the target.
VerCore RISC-V Design
Requirements Overview
Your task is to build VerCore, a RISC-V CPU core that supports RV32I and ZMMUL, with the following hardware interfaces, all synchronous to a master clock: * Instruction cache interface (32-bit datapath) * Data cache interface (32-bit datapath) * Other interface signals: clock input to core, reset_n input to core, asserted low.
VerCore should implement a simple 5-stage pipelined design, in-order, single-issue of course.
DO NOT support compressed instructions.
Implement the register file as flip flops. This allows register reads to happen any time during the cycle, but writes happen at the next rising clock edge.
You need to achieve a CPI <= 1.5. Your overall goal is to maximize your design’s score on CoreMark. Aim for a clock rate of 1.6 GHz.
You are responsible for both the RTL and the physical design. You should use the OpenROAD flow scripts to generate final GDSII output, along with area and timing information for this design. You should use the ASAP7 platform/PDK.
Assume that input signals will be valid 70% into the clock cycle. Make sure output signals are valid 20% into the clock cycle.
Testing
You have access to Spike, the RISC-V ISA simulator. Use this to build a cycle-by-cycle integration test and verify that the behavior of your module matches that of Spike.
A project from Verkor, a chip design startup. "Verkor is working with multiple of the top 10 fabless companies to deploy DC(Design Conductor; their AI agent for chip design) to accelerate their time to market".
I wonder how impressive this is for practitioners working on chip design. As a somewhat-adjacent amateur (I wrote some Verilog myself at all), it seems very impressive. I am a compiler practitioner (I was a committer to both LLVM and Rust) and I found Anthropic's Claude's C Compiler very impressive (to drop a name, Chris Lattner, the founder of LLVM, also found it impressive) and this seems similarly impressive.
I copied the full input to their system below. With that input and 12 hours, the system produced a decently working chip design. (While I can't see it myself lacking expertise in chip design, I expect it to be similarly "working" as Claude's C Compiler. CCC builds a bootable Linux kernel for multiple architectures, but it fails to reject programs with the simplest errors and has no diagnostics to speak of. It is in no way "production" quality.)
Note that apparent simplicity of input can be deceptive. If you think otherwise ask yourself whether you would have figured out the following problem from the paper:
VerCore RISC-V Design
Requirements Overview
Your task is to build VerCore, a RISC-V CPU core that supports RV32I and ZMMUL, with the following hardware interfaces, all synchronous to a master clock:
* Instruction cache interface (32-bit datapath)
* Data cache interface (32-bit datapath)
* Other interface signals: clock input to core, reset_n input to core, asserted low.
VerCore should implement a simple 5-stage pipelined design, in-order, single-issue of course.
DO NOT support compressed instructions.
Implement the register file as flip flops. This allows register reads to happen any time during the cycle, but writes happen at the next rising clock edge.
You need to achieve a CPI <= 1.5. Your overall goal is to maximize your design’s score on CoreMark. Aim for a clock rate of 1.6 GHz.
You are responsible for both the RTL and the physical design. You should use the OpenROAD flow scripts to generate final GDSII output, along with area and timing information for this design. You should use the ASAP7 platform/PDK.
Assume that input signals will be valid 70% into the clock cycle. Make sure output signals are valid 20% into the clock cycle.
Testing
You have access to Spike, the RISC-V ISA simulator. Use this to build a cycle-by-cycle integration test and verify that the behavior of your module matches that of Spike.